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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TimerBlox: Monostable Pulse Generator (One Shot) FEATURES
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DESCRIPTION
The LTC(R)6993 is a monostable multivibrator (also known as a "one-shot" pulse generator) with a programmable pulse width of 1s to 33.6 seconds. The LTC6993 is part of the TimerBloxTM family of versatile silicon timing devices. A single resistor, RSET, programs an internal master oscillator frequency, setting the LTC6993's time base. The output pulse width is determined by this master oscillator and an internal clock divider, NDIV , programmable to eight settings from 1 to 221. tOUT = NDIV *RSET * 1s, NDIV = 1, 8, 64,...,221 50k
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Pulse Width Range: 1s to 33.6 Seconds Configured with 1 to 3 Resistors Pulse Width Max Error: - <2.3% for Pulse Width > 512s - <3.4% for Pulse Width of 8s to 512s - <4.9% for Pulse Width of 1s to 8s Four LTC6993 Options Available: - Rising-Edge or Falling-Edge Trigger - Retriggerable or Non-Retriggerable Configurable for Positive or Negative Output Pulse Fast Recovery Time 2.25V to 5.5V Single Supply Operation 70A Supply Current at 10s Pulse Width 500s Start-Up Time CMOS Output Driver Sources/Sinks 20mA -40C to 125C Operating Temperature Range Available in Low Profile (1mm) SOT-23 (ThinSOTTM) and 2mm x 3mm DFN
The output pulse is initiated by a transition on the trigger input (TRIG). Each part can be configured to generate positive or negative output pulses. The LTC6993 is available in four versions to provide different trigger signal polarity and retrigger capability.
DEVICE LTC6993-1 LTC6993-2 LTC6993-3 LTC6993-4 INPUT POLARITY Rising-Edge Rising-Edge Falling-Edge Falling-Edge RETRIGGER No Yes No Yes
APPLICATIONS
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Watchdog Timer Frequency Discriminators Missing Pulse Detection Envelope Detection High Vibration, High Acceleration Environments Portable and Battery-Powered Equipment
The LTC6993 also offers the ability to dynamically adjust the width of the output pulse via a separate control voltage. The LTC6993 is available in the 6-lead SOT-23 (ThinSOT) and 6-lead 2mm x 3mm DFN packages.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and TimerBlox and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Envelope Detector
MODULATED CARRIER TRIG OUT SIGNAL ENVELOPE 3.3V 16s 0.1F RSET 800k SET DIV
69931234 TA01a
80kHz CARRIER TRIG 2V/DIV
LTC6993-2 GND V+
OUT 2V/DIV
50s/DIV
69931234 TA01b
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage (V+) to GND ........................................6V Maximum Voltage on Any Pin .................................. (GND - 0.3V) VPIN (V+ + 0.3V) Operating Temperature Range (Note 2) LTC6993C ............................................-40C to 85C LTC6993I .............................................-40C to 85C LTC6993H .......................................... -40C to 125C
Specified Temperature Range (Note 3) LTC6993C ................................................ 0C to 70C LTC6993I .............................................-40C to 85C LTC6993H .......................................... -40C to 125C Junction Temperature ........................................... 150C Storage Temperature Range .................. -65C to 150C Lead Temperature (Soldering, 10 sec) S6 Package ....................................................... 300C
PIN CONFIGURATION
TOP VIEW V+ 1 DIV 2 SET 3 7 6 OUT 5 GND 4 TRIG TRIG 1 GND 2 SET 3 TOP VIEW 6 OUT 5 V+ 4 DIV
DCB PACKAGE 6-LEAD (2mm x 3mm) PLASTIC DFN TJMAX = 150C, JA = 64C/W, JC = 10.6C/W EXPOSED PAD (PIN 7) CONNECTED TO GND, PCB CONNECTION OPTIONAL
S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150C, JA = 192C/W, JC = 51C/W
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) LTC6993IDCB-1#TRMPBF TAPE AND REEL LTC6993IDCB-1#TRPBF PART MARKING* LDXH LDXH LDXH LDXK LDXK LDXK LFMJ LFMJ LFMJ LFMM LFMM LFMM LTDXG LTDXG LTDXG PACKAGE DESCRIPTION 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead (2mm x 3mm) Plastic DFN 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 SPECIFIED TEMPERATURE RANGE 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C
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LTC6993CDCB-1#TRMPBF LTC6993CDCB-1#TRPBF LTC6993HDCB-1#TRMPBF LTC6993HDCB-1#TRPBF LTC6993CDCB-2#TRMPBF LTC6993CDCB-2#TRPBF LTC6993IDCB-2#TRMPBF LTC6993IDCB-2#TRPBF LTC6993HDCB-2#TRMPBF LTC6993HDCB-2#TRPBF LTC6993CDCB-3#TRMPBF LTC6993CDCB-3#TRPBF LTC6993IDCB-3#TRMPBF LTC6993IDCB-3#TRPBF LTC6993HDCB-3#TRMPBF LTC6993HDCB-3#TRPBF LTC6993CDCB-4#TRMPBF LTC6993CDCB-4#TRPBF LTC6993IDCB-4#TRMPBF LTC6993CS6-1#TRMPBF LTC6993IS6-1#TRMPBF LTC6993HS6-1#TRMPBF LTC6993IDCB-4#TRPBF LTC6993CS6-1#TRPBF LTC6993IS6-1#TRPBF LTC6993HS6-1#TRPBF LTC6993HDCB-4#TRMPBF LTC6993HDCB-4#TRPBF
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI) LTC6993CS6-2#TRMPBF LTC6993IS6-2#TRMPBF LTC6993HS6-2#TRMPBF LTC6993CS6-3#TRMPBF LTC6993IS6-3#TRMPBF LTC6993HS6-3#TRMPBF LTC6993CS6-4#TRMPBF LTC6993IS6-4#TRMPBF LTC6993HS6-4#TRMPBF TAPE AND REEL LTC6993CS6-2#TRPBF LTC6993IS6-2#TRPBF LTC6993HS6-2#TRPBF LTC6993CS6-3#TRPBF LTC6993IS6-3#TRPBF LTC6993HS6-3#TRPBF LTC6993CS6-4#TRPBF LTC6993IS6-4#TRPBF LTC6993HS6-4#TRPBF PART MARKING* LTDXJ LTDXJ LTDXJ LTFMH LTFMH LTFMH LTFMK LTFMK LTFMK PACKAGE DESCRIPTION 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 6-Lead Plastic TSOT-23 SPECIFIED TEMPERATURE RANGE 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C 0C to 70C -40C to 85C -40C to 125C
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL tOUT tOUT PARAMETER Output Pulse Width Pulse Width Accuracy (Note 4)
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
CONDITIONS NDIV 512
l
MIN 1
TYP 1.7 2.4
MAX 33.55 2.3 3.0 3.4 4.4 4.9 6.0 5.3 6.4
UNITS sec % % % % % % % % %/C %/C % %
8 NDIV 64
l
NDIV = 1 (LTC6993-1 or LTC6993-2)
l
3.6 4.0
l l l
NDIV = 1 (LTC6993-3 or LTC6993-4) tOUT/T Pulse Width Drift Over Temperature Pulse Width Change With Supply NDIV 512 NDIV 64 NDIV 512 8 NDIV 64 Pulse Width Jitter (Note 10) NDIV = 1 NDIV = 8 NDIV = 64 NDIV = 512 NDIV = 4096 tS Pulse Width Change Settling Time (Note 9) tMASTER = tOUT/NDIV V+ = 4.5V to 5.5V V+ = 2.25V to 4.5V V+ = 4.5V to 5.5V V+ = 2.7V to 4.5V V+ = 2.25V to 2.7V V+ = 5.5V V+ = 2.25V
0.006 0.008 -0.6 -0.4 -0.9 -0.7 -1.1 -0.2 -0.1 -0.2 -0.2 -0.1 0.85 0.45 0.20 0.05 0.20 0.03 6 * tMASTER 0.4 0.9
l l l l l
% % % %P-P %P-P %P-P %P-P %P-P %P-P s
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 ELECTRICAL CHARACTERISTICS
SYMBOL V+ IS(IDLE) PARAMETER Operating Supply Voltage Range Power-On Reset Voltage Supply Current (Idle) RL = , RSET = 50k, NDIV 64 RL = , RSET = 50k, NDIV 512 RL = , RSET = 800k, NDIV 64 V+ = 5.5V V+ = 2.25V V+ = 5.5V V+ = 2.25V V+ = 5.5V V+ = 2.25V Power Supply
l l l l l l l l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
CONDITIONS MIN 2.25 165 125 135 105 70 60 65 55 0.97 50 0 1.00 75 800 V+ 1.5 10 2.5 TRIG = 0V to V+ (Note 6) (Note 6) V+ = 2.7V to 5.5V V+ = 5.5V V+ = 5.5V V+ = 2.25V IOUT = -1mA IOUT = -16mA IOUT = -1mA IOUT = -16mA IOUT = -1mA IOUT = -8mA IOUT = 1mA IOUT = 16mA IOUT = 1mA IOUT = 10mA IOUT = 1mA IOUT = 8mA
l l l l l l l l l l l l l l
TYP
MAX 5.5 1.95 200 160 175 140 110 95 100 90 1.03
UNITS V V A A A A A A A A V V/C k V % nA pF
RL = , RSET = 800k, NDIV 512 V+ = 5.5V V+ = 2.25V Analog Inputs VSET VSET/T RSET VDIV VDIV/V+ Voltage at SET Pin VSET Drift Over Temperature Frequency-Setting Resistor DIV Pin Voltage DIV Pin Valid Code Range (Note 5) DIV Pin Input Current Digital I/O TRIG Pin Input Capacitance TRIG Pin Input Current VIH VIL IOUT(MAX) VOH High Level TRIG Pin Input Voltage Low Level TRIG Pin Input Voltage Output Current High Level Output Voltage (Note 7) Deviation from Ideal VDIV/V+ = (DIVCODE + 0.5)/16
l l l l l l
10 0.7 * V+ 0.3 * V+ 20 5.45 4.84 3.24 2.75 2.17 1.58 5.48 5.15 3.27 2.99 2.21 1.88 0.02 0.26 0.03 0.22 0.03 0.26 0.04 0.54 0.05 0.46 0.07 0.54
nA V V mA V V V V V V V V V V V V
VOL
Low Level Output Voltage (Note 7)
V+ = 5.5V V+ = 3.3V V+ = 2.25V
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 ELECTRICAL CHARACTERISTICS
SYMBOL tPD tWIDTH tARM tRETRIG tr tf PARAMETER Trigger Propagation Delay
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = , CLOAD = 5pF unless otherwise noted.
CONDITIONS V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 3.3V NDIV = 1 NDIV > 1 V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 5.5V V+ = 3.3V V+ = 2.25V V+ = 3.3V V+ = 3.3V MIN TYP 11 17 28 5 -4 10 50 1.1 1.7 2.7 1.0 1.6 2.4 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns
Minimum Recognized TRIG Pulse Width Recovery Time (LTC6993-1/LTC6993-3) Time Between Trigger Signals (LTC6993-2/LTC6993-4) Output Rise Time (Note 8)
Output Fall Time (Note 8)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC6993C is guaranteed functional over the operating temperature range of -40C to 85C. Note 3: The LTC6993C is guaranteed to meet specified performance from 0C to 70C. The LTC6993C is designed, characterized and expected to meet specified performance from -40C to 85C but it is not tested or QA sampled at these temperatures. The LTC6993I is guaranteed to meet specified performance from -40C to 85C. The LTC6993H is guaranteed to meet specified performance from -40C to 125C. Note 4: Pulse width accuracy is defined as the deviation from the tOUT equation, assuming RSET is used to program the pulse width. Note 5: See Operation section, Table 1 and Figure 2 for a full explanation of how the DIV pin voltage selects the value of DIVCODE.
Note 6: The TRIG pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can be estimated at any supply voltage using: VTRIG(RISING) 0.55 * V+ + 185mV and VTRIG(FALLING) 0.48 * V+ - 155mV Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrarily given a negative value. Note 8: Output rise and fall times are measured between the 10% and the 90% power supply levels with 5pF output load. These specifications are based on characterization. Note 9: Settling time is the amount of time required for the output to settle within 1% of the final pulse width after a 0.5x or 2x change in ISET . Note 10: Jitter is the ratio of the deviation of the output pulse width to the mean of the pulse width. This specification is based on characterization and is not 100% tested.
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4
V+ = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. tOUT Drift vs Temperature (NDIV 64)
1.5 1.0 0.5 DRIFT (%) DRIFT (%) 0 -0.5 -1.0 -1.5 -50 -25 RSET = 50k 3 PARTS 1.5 1.0 0.5 DRIFT (%) 0 -0.5 -1.0 -1.5 -50 -25
TYPICAL PERFORMANCE CHARACTERISTICS
tOUT Drift vs Temperature (NDIV 64)
RSET = 200k 3 PARTS 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -50 -25
tOUT Drift vs Temperature (NDIV 64)
RSET = 800k 3 PARTS
50 25 75 0 TEMPERATURE (C)
100
125
50 25 75 0 TEMPERATURE (C)
100
125
50 25 75 0 TEMPERATURE (C)
100
125
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69931234 G02
69931234 G03
tOUT Drift vs Temperature (NDIV 512)
1.5 1.0 0.5 DRIFT (%) DRIFT (%) 0 -0.5 -1.0 -1.5 -50 -25 RSET = 50k 3 PARTS 1.5 1.0 0.5
tOUT Drift vs Temperature (NDIV 512)
RSET = 200k 3 PARTS 1.5 1.0 0.5 DRIFT (%) 0 -0.5 -1.0
tOUT Drift vs Temperature (NDIV 512)
RSET = 800k 3 PARTS
0 -0.5 -1.0 -1.5 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
50 25 75 0 TEMPERATURE (C)
100
125
-1.5 -50 -25
50 25 75 0 TEMPERATURE (C)
100
125
69931234 G04
69931234 G05
69931234 G06
tOUT Drift vs Supply Voltage (NDIV = 1, Rising Edge)
1.0 0.8 0.6 0.4 DRIFT (%) DRIFT (%) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2 3 4 SUPPLY (V) RSET = 50k RSET = 200k RSET = 800k 5 6
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tOUT Drift vs Supply Voltage (NDIV = 1, Falling Edge)
1.0 0.8 0.6 0.4 0 -0.2 -0.4 -0.6 -0.8 -1.0 2 3 4 SUPPLY (V) RSET = 50k RSET = 200k RSET = 800k 5 6
69931234 G08
tOUT Drift vs Supply Voltage (NDIV > 1)
1.0 0.8 0.6 0.4 DRIFT (%) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2 3 RSET = 50k, NDIV = 8 RSET = 50k TO 800k, NDIV 512 RSET = 800k, NDIV = 8 4 SUPPLY (V) 5 6
69931234 G09
LTC6993-1/LTC6993-2 DIVCODE = 0 REFERENCED TO V+ = 4V
LTC6993-3/LTC6993-4 DIVCODE = 0 REFERENCED TO V+ = 4V
REFERENCED TO V+ = 4V
0.2
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL PERFORMANCE CHARACTERISTICS +
V = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. tOUT Error vs RSET (NDIV = 1, Rising Edge)
5 4 3 2 ERROR (%) ERROR (%) 1 0 -1 -2 -3 -4 -5 50 100 200 RSET (k ) 400 800
69931234 G10
LTC6993-1/LTC6993-2 DIVCODE = 0 3 PARTS
5 4 3 2
tOUT Error vs RSET (8 NDIV 64)
3 PARTS
5 4 3 2 ERROR (%) 1 0 -1 -2 -3 -4
tOUT Error vs RSET (NDIV 512)
3 PARTS
1 0 -1 -2 -3 -4 -5 50 100 200 RSET (k ) 400 800
69931234 G11
-5
50
100
200 RSET (k )
400
800
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tOUT Error vs RSET (NDIV = 1, Falling Edge)
5 4 3 2 ERROR (%) ERROR (%) 1 0 -1 -2 -3 -4 -5 50 100 200 RSET (k ) 400 800
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tOUT Error vs DIVCODE (Rising Edge)
5 4 3 2 ERROR (%) 1 0 -1 -2 -3 -4 -5 0 2 4 6 8 10 DIVCODE 12 14 LTC6993-1/LTC6993-2 RSET = 50k 3 PARTS 5 4 3 2 1 0 -1 -2 -3 -4 -5
tOUT Error vs DIVCODE (Falling Edge)
LTC6993-3/LTC6993-4 RSET = 50k 3 PARTS
LTC6993-3/LTC6993-4 DIVCODE = 0 3 PARTS
0
2
4
6 8 10 DIVCODE
12
14
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1.0 0.8 0.6 0.4
VSET Drift vs ISET
1.0 0.8 0.6 0.4 DRIFT (mV)
VSET Drift vs Supply Voltage
1.020 1.015 1.010 1.005 VSET (V) 1.000 0.995 0.990
VSET vs Temperature
3 PARTS
VSET (mV)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 REFERENCED TO ISET = 10A 10 ISET (A) 15 20
69931234 G16
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2 3 REFERENCED TO V+ = 4V 4 SUPPLY (V) 5
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0.985 6 0.980 -50 -25 75 0 25 50 TEMPERATURE (C) 100 125
69931234 G18
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4
V+ = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Typical VSET Distribution
2 LOTS DFN AND SOT-23 1274 UNITS 300 POWER SUPPLY CURRENT (A) 250 200 150 100 50 0
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Supply Voltage
"ACTIVE" = 50% TIMING DUTY CYCLE POWER SUPPLY CURRENT (A) RSET = 50k /1, ACTIVE RSET = 50k /1, IDLE RSET = 100k, /8, ACTIVE RSET = 100k, /8, IDLE CLOAD = 5pF RLOAD = 2 3 RSET = 800k, /512 6
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Supply Current vs Temperature
250 "ACTIVE" = 50% TIMING DUTY CYCLE RSET = 50k, /1, ACTIVE RSET = 50k, /1, IDLE RSET = 100k, /8, ACTIVE RSET = 100k, /8, IDLE 50 CLOAD = 5pF RLOAD = -25 RSET = 800k, /512
250
200 NUMBER OF UNITS
200
150
150
100
100
50
0 0.98
0.988
0.996 1.004 VSET (V)
1.012
1.02
4 5 SUPPLY VOLTAGE (V)
0 -50
0 25 50 75 TEMPERATURE (C)
100
125
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Supply Current vs TRIG Pin Voltage
250 POWER SUPPLY CURRENT (A) POWER SUPPLY CURRENT (A) 5V TRIG FALLING 5V TRIG RISING 250 200
Supply Current vs tOUT (5V)
ACTIVE CURRENT MEASURED WITH TRIGGER PERIOD = 2 * tOUT (50% DUTY CYCLE) /1 150 /8 /64 /512 250 POWER SUPPLY CURRENT (A) 200
Supply Current vs tOUT (2.5V)
ACTIVE CURRENT MEASURED WITH TRIGGER PERIOD = 2 * tOUT (50% DUTY CYCLE)
200
150
3.3V TRIG FALLING
3.3V TRIG RISING
150
/1
/8
/64
100 50 CLOAD = 5pF RLOAD = 0 0.2 0.6 0.4 VTRIG/V+ (V/V) 0.8 1.0
100 50 V+ = 5V CLOAD = 5pF RLOAD = 0 0.01 0.001
100 50 V+ = 2.5V CLOAD = 5pF RLOAD = 0 0.01 0.001
/512
0
ACTIVE IDLE 0.1 1 tOUT (ms) 10 100
ACTIVE IDLE 0.1 1 tOUT (ms) 10 100
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TRIG Threshold Voltage vs Supply Voltage
3.5 3.0 POSITIVE GOING RST PIN VOLTAGE (V) 2.5 JITTER (%P-P) 2.0 1.5 1.0 0.5 0 2 3 4 5 SUPPLY VOLTAGE (V) 6
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Peak-to-Peak Jitter vs tOUT
1.0 0.9 0.8 0.7 /1, 5.5V PEAK-TO-PEAK tOUT VARIATION MEASURED OVER 30s INTERVALS
Typical ISET Current Limit vs V+
1000 SET PIN SHORTED TO GND
800
NEGATIVE GOING
0.5 0.4 0.3 0.2 0.1 0 0.001
/1, 2.25V /8, 5.5V /512 /8, 2.25V 0.01 /64 0.1 1 tOUT (ms) /4096 10 100
ISET (A)
0.6
600
400
200
0
2
3
4 5 SUPPLY VOLTAGE (V)
6
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL PERFORMANCE CHARACTERISTICS +
V = 3.3V, RSET = 200k and TA = 25C unless otherwise noted. Trigger Propagation Delay (tPD) vs Supply Voltage
30 25 PROPAGATION DELAY (ns) RISE/FALL TIME (ns) 20 15 10 5 0 CLOAD = 5pF 3.0 2.5 OUTPUT RESISTANCE () 2.0 tRISE 1.5 tFALL 1.0 0.5 0
Rise and Fall Time vs Supply Voltage
CLOAD = 5pF 50 45 40 35 30 25 20 15 10 5 2 3 4 5 SUPPLY VOLTAGE (V) 6
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Output Resistance vs Supply Voltage
OUTPUT SOURCING CURRENT
OUTPUT SINKING CURRENT
2
3
4 5 SUPPLY VOLTAGE (V)
6
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0
2
3
4 5 SUPPLY VOLTAGE (V)
6
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PIN FUNCTIONS
(DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be bypassed directly to the GND pin with a 0.1F capacitor. DIV (Pin 2/Pin 4): Programmable Divider and Polarity Input. The DIV pin voltage (VDIV) is internally converted into a 4-bit result (DIVCODE). VDIV may be generated by a resistor divider between V+ and GND. Use 1% resistors to ensure an accurate result. The DIV pin and resistors should be shielded from the OUT pin or any other traces that have fast edges. Limit the capacitance on the DIV pin to less than 100pF so that VDIV settles quickly. The MSB of DIVCODE (POL) determines the polarity of the OUT pins. When POL = 0 the output produces a positive pulse. When POL = 1 the output produces a negative pulse. SET (Pin 3/Pin 3): Pulse Width Setting Input. The voltage on the SET pin (VSET) is regulated to 1V above GND. The amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current range is 1.25A to 20A. The output pulse will continue indefinitely if ISET drops below approximately 500nA,
and will terminate when ISET increases again. A resistor connected between SET and GND is the most accurate way to set the pulse width. For best performance, use a precision metal or thin film resistor of 0.5% or better tolerance and 50ppm/C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor may be used. Limit the capacitance on the SET pin to less than 10pF to minimize jitter and ensure stability. Capacitance less than 100pF maintains the stability of the feedback circuit regulating the VSET voltage.
V+ TRIG OUT V+ V+ C1 0.1F
LTC6993 GND
R1
SET RSET
DIV
69931234 PF
R2
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 PIN FUNCTIONS
(DCB/S6)
TRIG (Pin 4/Pin 1): Trigger Input. Depending on the version, a rising or falling edge on TRIG will initiate the output pulse. LTC6993-1 and LTC6993-2 are rising-edge sensitive. LTC6993-3 and LTC6993-4 are falling-edge sensitive. The LTC6993-2 and LTC6993-4 are retriggerable, allowing the pulse width to be extended by additional trigger signals that occur while the output is active. The LTC6993-1/ LTC6993-3 will ignore additional trigger inputs until the output pulse has terminated.
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground plane for best performance. OUT (Pin 6/Pin 6): Output. The OUT pin swings from GND to V+ with an output resistance of approximately 30. When driving an LED or other low impedance load a series output resistor should be used to limit source/sink current to 20mA.
BLOCK DIAGRAM (S6 package pin numbers shown)
5 R1 4 R2 TRIGGER/ RETRIGGER LOGIC V+ DIV 4-BIT A/D CONVERTER DIGITAL FILTER POL
1
TRIG
S OUTPUT POLARITY OUT
MASTER OSCILLATOR V 1s tMASTER = * SET ISET 50k
Q MCLK PROGRAMMABLE DIVIDER /1, 8, 64, 512, 4096, 215, 218, 221 R
6 tOUT
HALT OSCILLATOR IF ISET < 500nA ISET
POR
+ -
VSET = 1V SET 3 ISET RSET 1V
+ -
GND 2
69931234 BD
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 OPERATION
The LTC6993 is built around a master oscillator with a 1s minimum period. The oscillator is controlled by the SET pin current (ISET) and voltage (VSET), with a 1s/50k conversion factor that is accurate to 1.7% under typical conditions. 1s VSET tMASTER = * 50k ISET A feedback loop maintains VSET at 1V 30mV, leaving ISET as the primary means of controlling the pulse width. The simplest way to generate ISET is to connect a resistor (RSET) between SET and GND, such that ISET = VSET/RSET . The master oscillator equation reduces to: R tMASTER = 1s * SET 50k From this equation, it is clear that VSET drift will not affect the pulse width when using a single program resistor (RSET). Error sources are limited to RSET tolerance and the inherent pulse width accuracy tOUT of the LTC6993. RSET may range from 50k to 800k (equivalent to ISET between 1.25A and 20A). A trigger signal (rising or falling edge on TRIG pin) latches the output to the active state, beginning the output pulse. At the same time, the master oscillator is enabled to time the duration of the output pulse. When the desired pulse width is reached, the master oscillator resets the output latch. The LTC6993 also includes a programmable frequency divider which can further divide the frequency by 1, 8, 64, 512, 4096, 215, 218 or 221. This extends the pulse width duration by those same factors. The divider ratio NDIV is set by a resistor divider attached to the DIV pin. tOUT = NDIV VSET * * 1s 50k ISET NDIV *RSET * 1s 50k DIVCODE The DIV pin connects to an internal, V+ referenced 4-bit A/D converter that determines the DIVCODE value. DIVCODE programs two settings on the LTC6993: 1. DIVCODE determines the frequency divider setting, NDIV . 2. DIVCODE determines the polarity of OUT pin, via the POL bit. VDIV may be generated by a resistor divider between V+ and GND as shown in Figure 1.
2.25V TO 5.5V V+ LTC6993 DIV R2 GND
69931234 F01
R1
Figure 1. Simple Technique for Setting DIVCODE
Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the corresponding NDIV and POL values for the recommended resistor pairs. Other values may be used as long as: 1. The VDIV/V+ ratio is accurate to 1.5% (including resistor tolerances and temperature effects). 2. The driving impedance (R1||R2) does not exceed 500k. If the voltage is generated by other means (i.e., the output of a DAC) it must track the V+ supply voltage. The last column in Table 1 shows the ideal ratio of VDIV to the supply voltage, which can also be calculated as: VDIV V
+
=
DIVCODE + 0.5 1.5% 16
With RSET in place of VSET/ISET the equation reduces to: tOUT =
For example, if the supply is 3.3V and the desired DIVCODE is 4, VDIV = 0.281 * 3.3V = 928mV 50mV. Figure 2 illustrates the information in Table 1, showing that NDIV is symmetric around the DIVCODE midpoint.
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 OPERATION
Table 1. DIVCODE Programming
DIVCODE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 POL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 NDIV 1 8 64 512 4,096 32,768 262,144 2,097,152 2,097,152 262,144 32,768 4,096 512 64 8 1 Recommended tOUT 1s to 16s 8s to 128s 64s to 1.024ms 512s to 8.192ms 4.096ms to 65.54ms 32.77ms to 524.3ms 262.1ms to 4.194sec 2.097sec to 33.55sec 2.097sec to 33.55sec 262.1ms to 4.194sec 32.77ms to 524.3ms 4.096ms to 65.54ms 512s to 8.192ms 64s to 1.024ms 8s to 128s 1s to 16s R1 (k) Open 976 976 1000 1000 1000 1000 1000 887 681 523 392 280 182 102 Short R2 (k) Short 102 182 280 392 523 681 887 1000 1000 1000 1000 1000 976 976 Open VDIV /V+ 0.03125 0.015 0.09375 0.015 0.15625 0.015 0.21875 0.015 0.28125 0.015 0.34375 0.015 0.40625 0.015 0.46875 0.015 0.53125 0.015 0.59375 0.015 0.65625 0.015 0.71875 0.015 0.78125 0.015 0.84375 0.015 0.90625 0.015 0.96875 0.015
POL BIT = 0 10000 1000 100 tOUT (ms) 10 1 0.1 1 0.01 0.001 0V 0 0.5*V+ INCREASING VDIV 2 3 4 5 6 7 8 9 10
POL BIT = 1
11 12 13 14 15 V+
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Figure 2. Pulse Width Range and POL Bit vs DIVCODE
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 OPERATION
Monostable Multivibrator (One Shot) The LTC6993 is a monostable multivibrator. A trigger signal on the TRIG input will force the output to the active (unstable) state for a programmable duration. This type of circuit is commonly referred to as a one-shot pulse generator. Figures 3 details the basic operation. A rising edge on the TRIG pin initiates the output pulse. The pulse width (tOUT) is determined by the NDIV setting and by the resistor (RSET) connected to the SET pin. Subsequent rising edges on TRIG have no affect until the completion of the one shot and for a short rearming time (tARM) thereafter. To ensure proper operation, positive and negative TRIG pulses should be at least tWIDTH wide. The LTC6993-2 and LTC6993-4 allow the output pulse to be "retriggered". As shown in Figure 4, the output pulse will stay high until tOUT after the last rising-edge on TRIG. Successive trigger signals can extend the pulse width indefinitely. Consequtive trigger signals must be separated by tRETRIG to be recognized. Negative Trigger Versions In addition to the retrigger option, the LTC6993 family also includes negative input (falling-edge) versions. These four combinations are detailed in Table 2.
Table 2. Retrigger and Input Polarity Options
DEVICE LTC6993-1 LTC6993-2 LTC6993-3 LTC6993-4 INPUT POLARITY Rising-Edge Rising-Edge Falling-Edge Falling-Edge RETRIGGER No Yes No Yes
Output Polarity (POL Bit) Each variety of LTC6993 also offers the ability to invert the output, producing negative pulses. This option is programmed, along with NDIV, by the choice of DIVCODE. (The previous section describes how to program DIVCODE using the DIV pin).
tWIDTH TRIG tPD OUT tOUT tOUT tOUT
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tPD
tARM
Figure 3. Non-Retriggering Timing Diagram (LTC6993-1, POL = 0)
t WIDTH TRIG tPD OUT tOUT
t RETRIG
tPD
tPD
tPD
tOUT
tOUT
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Figure 4. Retriggering Timing Diagram (LTC6993-2, POL = 0)
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 OPERATION
Changing DIVCODE After Start-Up Following start-up, the A/D converter will continue monitoring VDIV for changes. Changes to DIVCODE will be recognized slowly, as the LTC6993 places a priority on eliminating any "wandering" in the DIVCODE. The typical delay depends on the difference between the old and new DIVCODE settings and is proportional to the master oscillator period. tDIVCODE = 16 * (DIVCODE + 6) * tMASTER A change in DIVCODE will not be recognized until it is stable, and will not pass through intermediate codes. A digital filter is used to guarantee the DIVCODE has settled to a new value before making changes to the output. However, if the output pulse is active during the transition, the pulse width can take on a value between the two settings.
DIV 500mV/DIV TRIG 2V/DIV OUT 2V/DIV LTC6993-1 V+ = 3.3V RSET = 200k 4s 256s 200s/DIV
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Start-Up Time When power is first applied, the power-on reset (POR) circuit will initiate the start-up time, tSTART . The OUT pin is held low during this time. The typical value for tSTART ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV): tSTART(TYP) = 500 * tMASTER During start-up, the DIV pin A/D converter must determine the correct DIVCODE before an output pulse can be generated. The start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to minimize the capacitance on the DIV pin so it will properly track V+. Less than 100pF will not extend the start-up time. The DIVCODE setting is recognized at the end of the startup up. If POL = 1, the output will transition high. Otherwise (if POL = 0) OUT simply remains low. At this point, the LTC6993 is ready to respond to rising/falling edges on the TRIG input.
V+
512s
TRIG tSTART (TRIG IGNORED) OUT POL = 0 POL = 1 tOUT 512s
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Figure 5a. DIVCODE Change from 0 to 2
DIV 500mV/DIV TRIG 2V/DIV OUT 2V/DIV
Figure 6. Start-Up Timing Diagram
4s 256s LTC6993-1 V+ = 3.3V RSET = 200k 200s/DIV
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Figure 5b. DIVCODE Change from 2 to 0
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION
Basic Operation The simplest and most accurate method to program the LTC6993 is to use a single resistor, RSET , between the SET and GND pins. The design procedure is a four step process. Step 1: Select the POL Bit Setting. The LTC6993 can generate positive or negative output pulses, depending on the setting of the POL bit. The POL bit is the DIVCODE MSB, so any DIVCODE 8 has POL = 1 and produces active-low pulses. Step 2: Select LTC6993 Version. Two input-related choices dictate the proper LTC6993 for a given application: * Is TRIG a rising or falling-edge input? * Should retriggering be allowed? Use Table 2 to select a particular variety of LTC6993. Step 3: Select the NDIV Frequency Divider Value. As explained earlier, the voltage on the DIV pin sets the DIVCODE which determines both the POL bit and the NDIV value. For a given output pulse width (tOUT), NDIV should be selected to be within the following range: tOUT t NDIV OUT 16s 1s (1) Step 4: Calculate and Select RSET. The final step is to calculate the correct value for RSET using the following equation: RSET = 50k tOUT * 1s NDIV (2)
Select the standard resistor value closest to the calculated value. Example: Design a one-shot circuit that satisfies the following requirements: * tOUT = 100s * Negative Output Pulse * Rising-Edge Trigger Input * Retriggerable Input * Minimum power consumption Step 1: Select the POL Bit Setting. For inverted (negative) output pulse, choose POL = 1. Step 2: Select the LTC6993 Version. A rising-edge retriggerable input requires the LTC6993-2. Step 3: Select the NDIV Frequency Divider Value. Choose an NDIV value that meets the requirements of Equation (1), using tOUT = 100s: 6.25 NDIV 100 Potential settings for NDIV include 8 and 64. NDIV = 8 is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 1 and NDIV = 8 requires DIVCODE = 14. Using Table 1, choose R1 = 102k and R2 = 976k values to program DIVCODE = 14. Step 4: Select RSET . Calculate the correct value for RSET using Equation (2): RSET = 50k 100s * = 625k 1s 8
To minimize supply current, choose the lowest NDIV value. However, in some cases a higher value for NDIV will provide better accuracy (see Electrical Characteristics). Table 1 can also be used to select the appropriate NDIV values for the desired tOUT . With POL already chosen, this completes the selection of DIVCODE. Use Table 1 to select the proper resistor divider or VDIV/V+ ratio to apply to the DIV pin.
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION
Since 625k is not available as a standard 1% resistor, substitute 619k if a -0.97% shift in tOUT is acceptable. Otherwise, select a parallel or series pair of resistors such as 309k and 316k to attain a more precise resistance. The completed design is shown in Figure 7.
TRIG OUT 2.25V TO 5.5V 0.1F SET RSET 625k DIV R1 102k DIVCODE = 14 R2 976k
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TRIG
OUT V+ V+ C1 0.1F
LTC6993 GND RMOD RSET
R1
VCTRL
SET
DIV R2
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LTC6993-2 GND V+
Figure 8. Voltage-Controlled Pulse Width
Digital Pulse Width Control The control voltage can be generated by a DAC (digital-toanalog converter), resulting in a digitally-controlled pulse width. Many DACs allow for the use of an external reference. If such a DAC is used to provide the VCTRL voltage, the VSET dependency can be eliminated by buffering VSET and using it as the DAC's reference voltage, as shown in Figure 9. The DAC's output voltage now tracks any VSET variation and eliminates it as an error source. The SET pin cannot be tied directly to the reference input of the DAC because the current drawn by the DAC's REF input would affect the pulse width.
Figure 7. 100s Negative Pulse Generator
Voltage-Controlled Pulse Width With one additional resistor, the LTC6993 output pulse width can be manipulated by an external voltage. As shown in Figure 8, voltage VCTRL sources/sinks a current through RMOD to vary the ISET current, which in turn modulates the pulse width as described in Equation (3). tOUT = NDIV *RMOD * 50k 1s RMOD VCTRL 1+ - RSET VSET (3)
TRIG V+
OUT V+ V+ C1 0.1F
LTC6993 0.1F GND
R1
1/2 LTC6078 0.1F V+
+ -
SET
DIV R2
69931234 F09
DIN P CLK CS/LD
VCC
REF VOUT RMOD
N *R tOUT = DIV MOD * 50k DIN = 0 TO 4095
1s RMOD DIN 1+ - RSET 4096
LTC1659 GND
RSET
Figure 9. Digitally Controlled Pulse Width
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION
ISET Extremes (Master Oscillator Frequency Extremes) When operating with ISET outside of the recommended 1.25A to 20A range, the master oscillator operates outside of the 62.5kHz to 1MHz range in which it is most accurate. The oscillator will still function with reduced accuracy for ISET < 1.25A. At approximately 500nA, the oscillator will stop. Under this condition, the output pulse can still be initiated, but will not terminate until ISET increases and the master oscillator starts again. At the other extreme, it is not recommended to operate the master oscillator beyond 2MHz because the accuracy of the DIV pin ADC will suffer. Settling Time Following a 2x or 0.5x step change in ISET , the output pulse width takes approximately six master clock cycles (6 * tMASTER) to settle to within 1% of the final value. An example is shown in Figure 10, using the circuit in Figure 8.
VCTRL 2V/DIV TRIG 5V/DIV OUT 5V/DIV PULSE WIDTH 2s/DIV LTC6993-1 V+ = 3.3V DIVCODE = 0 RSET = 200k RMOD = 464k tOUT = 3s AND 6s 20s/DIV
69931234 F10
Coupling Error The current sourced by the SET pin is used to bias the internal master oscillator. The LTC6993 responds to changes in ISET almost immediately, which provides excellent settling time. However, this fast response also makes the SET pin sensitive to coupling from digital signals, such as the TRIG input. Even an excellent layout will allow some coupling between TRIG and SET. Additional error is included in the specified accuracy for NDIV = 1 to account for this. Figure 11 shows that /1 supply variation is dependent on coupling from rising or falling trigger inputs and, to a lesser extent, output polarity. A very poor layout can actually degrade performance further. The PCB layout should avoid routing SET next to TRIG (or any other fast-edge, wide-swing signal).
1.0 0.8 0.6 0.4 DRIFT (%) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2 RSET = 50k NDIV = 1 3 LTC6993-3 POL = 0 LTC6993-3 POL = 1 LTC6993-1 POL = 1
LTC6993-1 POL = 0
4 SUPPLY (V)
5
6
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Figure 11. tOUT Drift vs Supply Voltage
Figure 10. Typical Settling Time
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION
Power Supply Current
POWER SUPPLY CURRENT (A) 250
The Electrical Characteristics table specifies the supply current while the part is idle (waiting to be triggered). IS(IDLE) varies with the programmed tOUT and the supply voltage. Once triggered, the instantaneous supply current increases to IS(ACTIVE) while the timing circuit is active. IS(ACTIVE) = IS(IDLE) + IS(ACTIVE) The average increase in supply current IS(ACTIVE) depends on the output duty cycle (or negative duty cycle, if POL = 1), since that represents the percentage of time that the circuit is active. IS(IDLE) and IS(ACTIVE) can be estimated using the equations in Table 2. Figure 12 shows how the supply current increases from IS(IDLE) as the input frequency increases. The increase is smaller at higher NDIV settings.
Table 2. Typical Supply Current
CONDITION NDIV 64 TYPICAL IS(IDLE)
V + * (NDIV * 7pF + 4pF ) tOUT + V+ + 2.2 *ISET + 50A 500k
V+ = 3.3V DUTY CYCLE = fIN * tOUT /1, RSET = 50k
200 /8, RSET = 50k /1, RSET = 100k /1, RSET = 800k
150
100 50 CLOAD = 5pF RLOAD = 20
0 IDLE
60 40 DUTY CYCLE (%)
80
100
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Figure 12. IS(ACTIVE) vs Output Duty Cycle
TYPICAL IS(ACTIVE)*
V+ * Duty Cycle * (NDIV * 5pF + 18pF + CLOAD ) tOUT V+ * Duty Cycle *CLOAD tOUT
NDIV 512
V + *NDIV * 7pF V+ + + 1.8 *ISET + 50A 500k tOUT
*Ignoring resistive loads (assumes RLOAD = )
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 APPLICATIONS INFORMATION
Supply Bypassing and PCB Layout Guidelines The LTC6993 is an accurate monostable multivibrator when used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. Figure 13 shows example PCB layouts for both the SOT-23 and DCB packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6993. These layouts are a guide and need not be followed exactly. 1. Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DCB package, C1's connection to GND is also simply done on the top layer. For the SOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that, C1's GND connection can be accomplished through multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1F ceramic capacitor. 2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make a direct, short connection. The SET pin is a current summing node and currents injected into this pin directly modulate the output pulse width. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling.
TRIG
OUT V+
LTC6993 GND C1 0.1F V+ R1
SET RSET V+ R1 V+ DIV R2 SET RSET C1 OUT GND TRIG
DIV R2
C1 TRIG GND SET RSET R2
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V+
OUT V+ DIV R1
DCB PACKAGE
TSOT-23 PACKAGE
Figure 13. Supply Bypassing and PCB Layout
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL APPLICATIONS
Missing Pulse Detector
25kHz INPUT 3.3V 0.1F R1 102k SET RSET 402k DIV R2 976k
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TRIG
OUT V+
LTC6993-2 GND
TRIG 2V/DIV
OUT 2V/DIV
64s
DIVCODE = 14 (NDIV = 8, POL = 1)
50s/DIV
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Use retriggerable one shot with output inverted. Output remains low as long as retrigger occurs within tOUT = 64s.
1.5ms Radio Control Servo Reference Pulse Generator
5V R7 10k RESET = OPEN RUN = GND (CLOSED) 20ms FRAME RATE GENERATOR RST OUT 5V V+ R4 976k R5 102k R6 10k C1 0.01F 1.5ms REFERENCE PULSE TRIG OUT 5V R1 1M SET R8 143k 1.5ms CAL TRIM DIV R2 280k
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20ms PERIOD
1.5ms PULSE
LTC6991 GND
LTC6993-1 GND V+
C2 0.01F
SET R3 121k
DIV
Pulse Delay Generator
100s DELAY GENERATOR PULSE IN TRIG OUT 5V R4 182k SET R6 78.7k DIV R5 976k R3 61.9k C1 0.01F V+ 10s OUTPUT PULSE GENERATOR TRIG OUT 5V R1 976k SET DIV R2 102k C2 0.1F V+ OUT
LTC6993-1 GND
LTC6993-1 GND
10s PULSE IN 100s DELAY 10s PULSE OUT
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL APPLICATIONS
RC Servo Pulse Generator Controlled Retrigger Lockout Time Interval
1.5ms PULSE GENERATOR TRIG OUT 5V R1 1M R2 280k C2 0.1F TRIGGER PULSE IN 1.5ms PULSE OUT 20ms RETRIGGER LOCKOUT V+ PULSE OUT R9 10k
TRIGGER
LTC6993-1 GND
M1 2N7002
SET R3 147k
DIV
20ms RETRIGGER LOCKOUT INTERVAL OUT R5 100k 5V 0.1F R6 1M R7 392k V
+
TRIG
RETRIGGER LOCKOUT TIME
LTC6993-1 GND
DIV
SET
R4 243k
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Staircase Generator with Reset
R8 4.99k PULSE FREQUENCY-TO-VOLTAGE CONVERTER 5V 0.1F D1 1N4148 R11 2k C1 1F R9 100k RETRIGGERABLE STAIRCASE RESET PULSE GENERATOR TRIG OUT 5V R1 280k R2 1M C2 0.1F V+ R7 10k 5V 0.1F
PULSES IN
R6 20k
U4 2N7002 RESET STAIRCASE RESET RAMP RESET
LTC6993-2 GND
R3 147k
SET
DIV
+
STAIRCASE OUT PULSES IN RESETS AFTER 1.5ms IF NO PULSES APPLIED
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+
R10 10k
U2 LT1490
-
U3 LT1490
STAIRCASE OUT VOUT
-
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL APPLICATIONS
Pulse Stretcher
5V R4 4.99k U2 LT1009 2.5V Q4 2N2219A
R1 10k
VOLTAGE VARIABLE OUTPUT PULSE WIDTH TRIG 5V 0.1F OUT V+ PULSE OUT STRETCHED PULSE OUT 5V
LTC6993-3 GND
Q1 2N2907
Q2 2N2907 RAMP R6 C1 10k 2200pF
U4 LT1638
R16 140k R13 113k
R14 976k R15 102k
C4 0.1F
Q3 2N2219A
R7 10k RAMP VOLTAGE PROPORTIONAL TO INPUT PULSE WIDTH
PULSE IN
1s TO 10s INPUT PULSE WIDTH
TRIG
OUT V+
500s RAMP RESET TIMER 5V R2 182k R5 976k
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LTC6993-1 GND
R3 392k
SET
DIV
On-Time Programmable Pulsed Solenoid Driver
24V 5 SECONDS ON TRIGGER IN TRIGGER TRIG OFF OUT
+
D1 1N4004 R4 2k 5V R1 1M R2 887k
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100mA SOLENOID DANFOSS 042 N024D TYPE AK024D Q1 2N2219A
LTC6993-1 GND V
C2 0.1F R3 118k
R3 118k
SET
DIV
22
+
C2 0.1F ENABLE PULSES
-
SET
DIV
Safety Time-Out Relay Driver
TIMED (5s) TURN-OFF AFTER LOSS OF INPUT PULSES RUN RESET TRIG OUT V+ R1 1M SET DIV R2 887k
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12V L D1 1N4148 R4 15k 5V C2 0.1F C NO 1 COTO 1022 RELAY 9001-12-01
Q1 2N2219A
LTC6993-2 GND
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LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 PACKAGE DESCRIPTION
(Reference LTC DWG # 05-08-1715 Rev A)
2.00 0.10 (2 SIDES) 0.70 0.05 R = 0.115 TYP 0.40 0.10 4 6
DCB Package 6-Lead Plastic DFN (2mm x 3mm)
R = 0.05 TYP
3.55 0.05
1.65 0.05 (2 SIDES) PACKAGE OUTLINE PIN 1 BAR TOP MARK (SEE NOTE 6)
3.00 0.10 (2 SIDES)
1.65 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 x 45 CHAMFER 3 1
(DCB6) DFN 0405
2.15 0.05
0.25 0.05 0.50 BSC 1.35 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.200 REF
0.75 0.05
0.25 0.05 0.50 BSC
1.35 0.10 (2 SIDES) 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
(Reference LTC DWG # 05-08-1636)
0.62 MAX 0.95 REF 2.90 BSC (NOTE 4)
S6 Package 6-Lead Plastic TSOT-23
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 - 1.75 (NOTE 4) PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR
0.95 BSC 0.80 - 0.90
0.30 - 0.45 6 PLCS (NOTE 3)
0.20 BSC DATUM `A' 1.00 MAX
0.01 - 0.10
0.30 - 0.50 REF
NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193
0.09 - 0.20 (NOTE 3)
1.90 BSC
S6 TSOT-23 0302 REV B
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6993-1/LTC6993-2 LTC6993-3/LTC6993-4 TYPICAL APPLICATION
Consecutive Test Sequencer
START TEST SEQUENCE 2s TO 30s DELAY TRIG OUT 5V R10 25k DELAY ADJUST 30s R9 274k 2s LTC6994-1 GND SET R1 63.4k V+ DIV 5V 0.1F R2 1000k R3 887k DELAY TRIG OUT LTC6993-1 GND SET R6 191k V+ DIV 5V 0.1F TEST 1 TRIG OUT LTC6993-3 GND SET R7 191k V+ DIV 5V 0.1F TEST 2 TRIG OUT LTC6993-3 GND SET R8 191k
69931234 TA10
TEST 3
5V 0.1F R5 1000k R4 681k
V+ DIV
SHARED DIV PIN BIASING FOR EQUAL ONE-SHOT TIMERS
START DELAY
TEST 1 TEST 2 TEST 3
ONE SECOND DURATION SEQUENTIAL TEST PULSES AFTER AN ADJUSTABLE DELAY TIME
RELATED PARTS
PART NUMBER LTC1799 LTC6900 LTC6906/LTC6907 LTC6930 LTC6990 LTC6991 LTC6992 LTC6994 DESCRIPTION 1MHz to 33MHz ThinSOT Silicon Oscillator 1MHz to 20MHz ThinSOT Silicon Oscillator 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator Fixed Frequency Oscillator, 32.768kHz to 8.192MHz TimerBlox: Voltage-Controlled Silicon Oscillator TimerBlox: Resettable Low Frequency Oscillator TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM) TimerBlox: Delay Block/Debouncer COMMENTS Wide Frequency Range Low Power, Wide Frequency Range Micropower, ISUPPLY = 35A at 400kHz 0.09% Accuracy, 110s Start-Up Time, 105A at 32kHz Fixed-Frequency or Voltage-Controlled Operation Clock Periods up to 9.5 hours Simple PWM with Wide Frequency Range Delay Rising Edge, Falling Edge or Both Edges
69931234f
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
LT 1010 * PRINTED IN USA
FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORA TION 2010

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